As devices have been scaled, the channel length in the semiconductor devices has become smaller and smaller. When the semiconductor devices have a gate size of 0.13 micron, for example, the extremely short channel length generates a hot carrier effect. For example, as the channel length is made smaller, it's associated electric field increases. As the electric field increases, the force on the electrons increases causing them to move faster and faster in the channel. Such energetic electrons are referred to as “hot carriers”.
There is a potential barrier between the silicon substrate and the silicon dioxide (SiO2) gate oxide of a metal oxide semiconductor (MOS) transistor. As electrons flow in the channel, some scattering of the electrons in the lattice of the silicon substrate occurs due to interface states and fixed charges (interface defects). As electron scattering increases, the mobility of the hot carriers is reduced, thereby reducing the current flowing through the channel. Over a period of time, hot carriers degrade the silicon bonds with an attendant increase in electron scattering due to an increase in interface and bulk defects. As a result, the transistor slows down over a period of time.
The lifetime of the transistor is normally measured as the length of time a device operates until a 10% degradation in the operation of the device is reached. This may be measured, for example, as a 10% reduction in the current flow in the channel. For example, if a transistor designed for a 10 milliamps current in 3.3 volt technology is reduced to less than 9 milliamps within one year, the semiconductor device is said to have a hot carrier lifetime of one year. The hot carrier lifetime constraints in an NMOS device limit the current drive that can be used in a given technology. By improving the hot carrier lifetime, the current drive can be increased, thereby increasing the operating speed of a device, such as a microprocessor.
In order to estimate the hot carrier degradation, hot carrier reliability has been evaluated by stress acceleration experiments under DC conditions with respect to a MOS transistor. Using the results of these tests, production processes are optimized to obtain an improved lifetime. Various models have been used, and various equations have been derived for use in extracting estimated lifetimes from experimental data obtained in stress acceleration experiments. However, most such methods have relied upon a small number of samples, and so have suffered from a variability that detracted from the reliability of the resulting estimates.
Therefore, a need remains for a method and apparatus which will allow circuit designers and fabricators to predict the lifetime of such devices. Specifically, there is a need for an improved comprehensive DC HCI lifetime projection model, and an improved method and apparatus for predicting semiconductor lifetime.